1. Field of the Disclosure
The present disclosure relates to an organic light-emitting diode (OLED) display device, and more particularly, to an array substrate for a gate-in-panel-type (GIP) OLED display device, which may minimize parasitic capacitance of a signal input unit.
2. Discussion of the Related Art
An organic light-emitting diode (OLED) display device, which is a flat panel display (FPD), has high luminance and a low operating voltage. Also, the OLED display device, which is an emissive display, has a high contrast ratio, may embody an ultrathin display, has a response time of about several microseconds (us) to facilitate formation of moving images, has an unlimited viewing angle, may be stably driven even at a low temperature, and be driven at a low direct-current (DC) voltage of about 5V to about 15V. Therefore, the OLED display device may facilitate the manufacture and design of a driver circuit.
Accordingly, the OLED display device having the above-described advantages has lately been employed for various information and technology (IT) apparatuses, such as televisions (TVs), monitors, and cellular phones.
Hereinafter, a basic structure of the OLED display device will be described in further detail.
FIG. 1 is a schematic cross-sectional view of a related art OLED display device.
A typical OLED display device 1 may broadly include an array substrate 10 including an array device and an OLED E, and an opposite substrate 70 disposed opposite the array substrate 10 and serving an encapsulation function. The array device may include a switching thin film transistor (TFT) (not shown) connected to gate and data lines (not shown), and a driving TFT (DTr) connected to the OLED E. The OLED E may include a first electrode 47 connected to the driving TFT DTr, an organic emission layer (EML) 55, and a second electrode 580.
To complete the OLED display device 1 having the above-described construction, a driver unit having a driver circuit configured to drive the OLED E is required.
In general, the driver unit is embodied on a printed circuit board (PCB) (not shown). In this case, the PCB is divided into a gate PCB (not shown) connected to a plurality of gate lines (not shown) formed on the array substrate 10, and a data PCB (not shown) connected to a plurality of data lines (not shown).
Meanwhile, the gate PCB and the data PCB may be respectively mounted on a gate pad portion and a data pad portion using a tape carrier package (TCP), or by interposing a flexible printed circuit (FPC) therebetween. The gate pad portion may be formed on one side surface of the array substrate 10 for the OLED display device and connected to the gate line. Also, the data pad portion is typically formed on a top side surface orthogonal to the one side surface on which the gate pad is formed, and connected to the data line.
However, when the PCB is divided into the gate PCB and the data PCB and mounted on the gate pad portion and the data pad portion as in the related art, the volume and weight of the PCB may increase.
Accordingly, to solve this problem, a gate-in-panel (GIP)-type OLED display device in which gate and data PCBs are integrated into a single PCB and mounted on only one side surface of an array substrate, has been proposed.
FIG. 2 is a plan view of an array substrate for a related art GIP-type OLED display device, and FIG. 3 is an enlarged view of region A of FIG. 2.
Referring to FIGS. 2 and 3, an array substrate 40 for a GIP-type OLED display device may broadly include a display region AA configured to display an image, a pad portion PA disposed above the display region AA, first and second gate circuit units C1 and C2 provided in a non-display region NA disposed on one side of the display region AA, and first and second signal input units S1 and S2 connected to the gate circuit units C1 and C2.
More specifically, a gate line 73, a data line 76, a TFT Tr, and a first electrode 78 may be provided on the display region AA. The gate line 73 and the data line 76 may intersect each other and define a pixel region P. The TFT Tr may be connected to each of the gate line 73 and the data line 76 and serves as a switching device. The first electrode 78 is connected to the TFT Tr.
In addition, a data pad DP and a plurality of gate pads GP may be formed on the pad portion PA disposed above the display region AA. The data pad DP may be connected to the data line 76 formed on the display region AA, and connected to an external PCB (not shown). The gate pads GP may be connected to a plurality of clock signal lines CLK1 to CLK13, and a plurality of gate signal lines VGH, VGL, and VST formed in the first and second signal input units S1 and S2.
Furthermore, a plurality of circuit blocks CB1 and CB2 may be provided on the first and second gate circuit units C1 and C2. The circuit blocks CB1 and CB2 may be connected to one another and separated into respective pixel lines PL including a plurality of pixel regions P connected to the same gate line 73. Each of the plurality of circuit blocks CB1 and CB2 may include a combination of a plurality of switching devices, a plurality of driver devices, and a plurality of capacitors. Each of the circuit blocks CB1 and CB2, which belongs to each of the pixel lines PL, may be internally divided again into one or two partial circuit blocks PB1 and PB2. In this case, the plurality of circuit blocks CB1 and CB2 provided in the same pixel line PL may be connected to one another by the gate line 73 and a subsidiary line (not shown) provided in the pixel line PL.
The gate circuit units C1 and C2 and the signal input units S1 and S2 will be described in further detail.
In the array substrate 40 for the related art GIP-type OLED display device, the first signal input unit S1 and the first gate circuit unit C1 may sequentially alternate with the second signal input unit S2 and the second gate circuit unit C2 on the non-display region NA disposed on one side of the display region AA.
In addition, a first partial circuit block PB1 and a second partial circuit block PB2 may be provided in the first gate circuit unit C1, which belongs to each of the pixel lines PL, in a widthwise direction of the corresponding pixel line PL.
In this case, the first partial circuit block PB1 becomes an 8-phase type requiring eight different clock signals, while the second partial circuit block PB2 becomes a 5-phase type requiring five different clock signals.
Furthermore, the first signal input unit S1 may include first through eight clock lines CLK1 to CLK8 configured to input signals to the first partial circuit block PB1, ninth to thirteenth clock lines CLK9 to CLK13 configured to input signals to the second partial circuit block PB2, a gate high signal line VGH, a gate low signal line VGL, and a storage signal line VST configured to apply a storage voltage.
Although an enlarged view is not presented, the second gate circuit unit C2 and the second signal input unit S2 may have the same configurations as the first gate circuit unit C1 and the first signal input unit C1, respectively.
However, in the above-described array substrate 40 for the related art GIP-type OLED display device, each of the first and second circuit blocks CB1 and CB2, which belongs to each of the pixel lines PL, is internally divided into the first and second partial circuit blocks PB1 and PB2 in the widthwise direction of the corresponding pixel line PL. Thus, since there are plenty of intersected and overlapped portions between the clock lines CLK1 to CLK13 and a plurality of first connection lines CL configured to connect the clock lines CLK1 to CLK13 provided in the first and second signal input units S1 and S2, the first and second signal input units S1 and S2 may have very large parasitic capacitances.
In a specific example, the 8-phase-type first partial circuit block PB1 may be connected to the first through eighth clock lines CLK1 to CLK8, while the 5-phase-type second partial circuit block PB2 may be connected to the ninth to thirteenth clock lines CLK9 to CLK13. In this case, referring to the drawings, all of a plurality of first connection lines CL connected to a plurality of elements (not shown) included in the first partial circuit block PB1 are basically configured to intersect the ninth through thirteenth clock lines CLK9 to CLK13 connected to the second partial circuit block PB2, so that relatively large parasitic capacitances may be generated.
Accordingly, since a parasitic capacitance accumulates from a first pixel line PL1 toward an n-th pixel line PLn due to the parasitic capacitances generated between the plurality of clock lines CLK1 to CLK13 and the plurality of first connection lines CL, a difference between clock signals passing through each of the clock lines CLK1 to CLK13 may occur.
As a result, the first and second gate circuit units C1 and C2 disposed relatively close to the pad portion PA on which an external PCB (not shown) is mounted, may be normally driven to output normal images to the display region AA through the pixel line PL connected to the first and second gate circuit units C1 and C2. However, the first and second gate circuit units C1 and C2 disposed relatively far away from the pad portion PA cannot properly output signals due to the accumulated parasitic capacitance, so the pixel line PL connected to the first and second gate circuit units C1 and C2 cannot output normal images to the display region AA to degrade display quality.